Stray-insensitive sample-delay-hold buffers for high-frequency switched-capacitor filters

Two high-frequency switched-capacitor sample-delay-hold (SDH) buffers are presented. The circuits provide a correct transition from the continuous-time to the discrete-time domain or vice versa. Experimental results show an excellent frequency behavior for clock frequencies up to 25 MHz

A CMOS class-AB transconductance amplifier for switched-capacitor applications

A CMOS operational transconductance amplifier (OTA) using a fully differential single-stage core OTA as the input stage and a differential to single current converter as the output stage, each biased at a separate current level, is presented. A large gain-bandwidth product (2.7 MHz) and a high slew-rate (5 V/μs) can be obtained by applying a large bias current to the core OTA. Due to the class-AB operation of the output stage, a high output impedance can be obtained by applying a small bias current to the output stage, resulting in a high DC-gain (61.6 dB). When the performance of this class-AB OTA is compared with that of basic single-stage OTAs it is found that the output impedance of the class-AB OTA is increased without limiting the bandwidth or slew-rat

A CMOS class-AB transconductance amplifier for switched-capacitor applications

A CMOS operational transconductance amplifier (OTA) using a fully differential single-stage core OTA as the input stage and a differential to single current converter as the output stage, each biased at a separate current level, is presented. A large gain-bandwidth product (2.7 MHz) and a high slew-rate (5 V/μs) can be obtained by applying a large bias current to the core OTA. Due to the class-AB operation of the output stage, a high output impedance can be obtained by applying a small bias current to the output stage, resulting in a high DC-gain (61.6 dB). When the performance of this class-AB OTA is compared with that of basic single-stage OTAs it is found that the output impedance of the class-AB OTA is increased without limiting the bandwidth or slew-rat

Spectral analysis of double-sampling switched-capacitor filters

The double-sampling scheme (DSS) design technique is suitable for the realization of high-frequency switched-capacitor (SC) filters. This design technique effectively doubles the applicable frequency range of standard bi-phase SC filters. In practice, the particular nonideal properties of the double-sampling scheme result mainly in parasitic sidebands in the output spectrum. The DSS design technique is described, and a spectral analysis of double-sampling SC filters, including the nonideal properties, is given. With these results, the precise specifications for the pre- (anti-aliasing) and postfilter are derived. An excellent match between the analytical description and experimental results is found for a linear fifth-order elliptic double-sampling SC low-pass filter designed for video frequency application

Stray-insensitive switched-capacitor sample-delay-hold buffers for video frequency applications

Two video frequency switched-capacitor sample-delay-hold (SDH) buffers are presented. The circuits provide a correct transition from the continuous-time to the discrete-time domain or vice versa. Experimental results show an excellent frequency behaviour for clock frequencies up to 25 MH